Power supplies for generating a predetermined voltage/current for a given application can make abnormal demands on the line supply caused by the harmonic content of the current drawn from the line. In particular, a high third harmonic content can give a large neutral current which can place unacceptable loads on the line supply transformer. To compensate for this problem, power factor correction (PFC) circuits have been developed to reduce the harmonic content. A conventional AC to DC power converter typically includes a boost converter for power factor correction of the input bulk voltage generated from the AC input power source and a DC to DC converter to convert the unregulated bulk voltage into an output voltage that satisfies the voltage regulation and transient response requirements of the power converter. The power factor correction circuit modifies the current waveform to reduce the harmonics and thus enable the current waveform to more closely define a sinusoidal waveform that is in phase with the line voltage.
FIG. 1 shows a schematic diagram of a prior art PFC boost converter 10. Included in converter 10 is an input voltage sampling circuit that includes two filter capacitors 18 and 24. A rectified input line voltage Vin from a conventional bridge rectifier (not shown) is applied at input terminals 2 and 4. The PFC boost converter includes a boost (choke) inductor 32, an electronic switch 30, a diode 34, and a PFC controller 28 to produce an output voltage across capacitor 40 connected between output terminals 6 and 8. The boost converter 10 uses a switching technique to boost the rectified input voltage to a regulated DC output voltage for delivery to a load (not shown) via terminals 6 and 8. Switch 30 is typically a FET having a control input as seen in FIG. 1.
PFC controller 28 has an output pin (GDRV) connected to the control input of switch 30 to control the state of the switch 30. PFC controller 28 includes an enable input pin (ENABLE) that is used to enable the switching of switch 30. PFC controller 28 has a voltage feedback input pin (VFB) to which is applied a voltage from a voltage divider formed by series resistors 48 and 52 connected across the output terminals 6 and 8. PFC controller 28 compares a portion of the boosted output DC voltage from the terminals 6 and 8 to a reference voltage input (not shown) to maintain the desired regulated output DC voltage. In addition to this regulation function, the purpose of the PFC controller 28 is to modify the input current waveform to reduce the harmonics and thus enable the current waveform to more closely define a sinusoidal waveform that is in phase with the line voltage. PFC controller 28 has an input AC (IAC) pin. The IAC pin for PFC controller 28 may be connected to the rectified input voltage at terminals 2 and 4 using a voltage divider circuit comprising resistors 12 and 14. The IAC pin input generates, via a multiplier, a current reference for a current amplifier in PFC controller 28 (details not shown). One exemplary PFC controller for use in converter 10 is manufactured by STMicroelectronics under their model number L4981. The switching frequency for the L4981 is in the range of 100 kHz. Other suitable controller devices are available from other manufacturers. For simplicity of explanation, the circuit has been shown based upon the L4981 PFC controller.
A comparator 26 is included to provide a signal input to the enable input of the PFC controller 28 as a function of the input voltage and output voltage. For the L4981 PFC controller, the enable input is also referred to as the sync input. The output voltage between terminals 6 and 8 is divided by a voltage divider formed by series resistors 36 and 38 to generate a voltage applied to the negative input of comparator 26. The positive input of comparator 26 receives a sampled input voltage at a node 44 from an input voltage sampling circuit. For the prior art converter 10, the input voltage sampling circuit comprises two filter capacitors 18 and 24. The sampling circuit includes a series combination of a resistor 16 and the filter capacitor 18 connected between input terminals 2 and 4. Resistor 16 and filter capacitor 18 are connected together at node 46. A resistor 20 is connected in series with a parallel combination of a resistor 22 and filter capacitor 24 between node 46 and terminal 4.
In general, power factor correction circuits are designed to work over all usual line voltages used worldwide, typically 65 VAC–265 VAC and provide a well regulated output voltage for input to a bulk converter of standard design which performs the required voltage/current conversion for a particular application. It is desirable to provide a protection circuit, also referred to herein as an inhibit circuit, to protect the boost converter from conditions such as input voltage surges that can otherwise cause failure, and to prevent unnecessary down time of the boost converter after a power failure or on startup. For one aspect of such protection, it is desired that the converter quickly recover after a momentary loss of the input voltage so that the down time of the power supply is reduced.
The prior art protection circuit comprises the comparator 26 and the above-discussed circuits that provide inputs thereto. In operation, capacitors 18 and 24 of converter 10 determine the average of the input voltage sine wave, such that the output voltage is compared by comparator 26 to a filtered, averaged, non-real-time voltage representation of the rectified input voltage. That is, the circuit is designed to determine the peak of the input sine wave voltage by using a capacitor filter to first find the “average” voltage on the input, and to only allow boost to begin when the output voltage rises near to, or above, this averaged input peak voltage. The result is excessive downtime for the PFC boost circuit. For recovery after a power loss, for example, converter 10 starts up slowly due to the fact that the circuit waits at least a few cycle times until the output voltage is higher than the input sine wave voltage and only thereafter allows boost to start. In the case of short glitches appearing on the input power line, the protection circuit for converter 10 fails to adequately protect the PFC boost converter since the response time of the filtered circuit is too slow to provide the required protection.
A need exists, therefore, for the PFC boost converter to recover more quickly after a momentary loss of the input voltage so that the downtime of the power supply is reduced.
In the case of a sudden high voltage surge on the input voltage line, the converter 10 in FIG. 1 has the drawback that it causes the PFC to latch in order to avoid damage to the power supply unit. The converter in FIG. 1 latches the PFC to prevent saturation of the boost choke and to avoid damage to the power supply unit. Thus, in the case of high voltage surges at the input, the prior art circuit shuts down the operation of the unit rather than providing a way in which circuit operation can be maintained during such conditions. A circuit is therefore needed to quickly inhibit the boost function of the PFC controller thereby disabling boost and protecting the circuit from burning out. Although PFC boost converters using PFC controllers such as the L4981 are fast enough to enable boost during fractions of the input voltage half-sine wave, no prior art circuit has utilized this feature to speed up boost response. A circuit is therefore needed to enable boost to be provided in real time in order to reduce the down time of the power supply, and to also protect the PFC boost converter in real time when short high voltage glitches appear on the input voltage line.